The present invention relates to the field of computer processors, and more particularly, to performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching.
An Out of Order (OoO) processor typically contains multiple execution pipelines that may execute instructions in a different order than what the program sequence (or “program order”) specifies in order to maximize the average instruction per cycle rate by reducing data dependencies and maximizing utilization of the execution pipelines allocated for various instruction types. Results of instruction execution are typically held temporarily in physical registers of one or more register files of limited depth. An OoO processor typically employs register renaming to avoid unnecessary serialization of instructions due to the reuse of a given architected register by subsequent instructions in the program order.
Various methods and systems have been developed for decoding and optimizing instructions for execution by an OoO processor. However, decoding instructions and performing additional decode time instruction optimization can cause an increase in the power consumption and heat dissipation of a microprocessor. In addition, decoding instructions and performing additional decode time instruction optimization can also require the introduction of additional pipeline stages into a microprocessor.
In instances where a series of instructions are required to be executed repeatedly, such as with a program loop or recursive function, current methods for decoding instructions and performing additional decode time instruction optimization preform decoding and optimization operations repeatedly prior to execution of the instructions. This repetition of decoding and optimization for the same serious of instructions causes unnecessary power and heat dissipation, and execution delay due to the optimizations being performed.